1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly it relates to a technique of controlling a sense amplifier in a dynamic random access memory (DRAM) in a data write operation thereof and thereby improving performance thereof in the write operation
2. Description of the Related Art
A typical DRAM device includes a write amplifier circuit which amplifies complementary write data input from the outside of the device and transmits the amplified data via complementary data lines to a selected pair of complementary bit lines, together with a sense amplifier provided for each pair of a plurality of pairs of bit lines. In a general design of the device, the current drive ability of each transistor used in the write amplifier circuit is selected to be much higher than that of each transistor used in the individual sense amplifier. This is because, where the current drive ability of each transistor used in the individual sense amplifier is designed to be relatively high, an area occupied by the respective sense amplifiers n a chip is increased.
In this connection, a prior art DRAM device carries out its write operation utilizing the difference between the above current drive abilities. In this case, there is no problem where the device writes data of a logical level same as data latched in the sense amplifier.
A problem occurs, however, where the device writes data of a logical level opposite to data latched in the sense amplifier. In this case, the device must invert the latched state of the sense amplifier with the sense amplifier being activated. Accordingly, past of the write current fed from the write amplifier circuit leaks through the activated sense amplifier until the latched state is perfectly inverted. Thus, a problem occurs in that power is uselessly dissipated and it takes considerable time to invert the latched state of the sense amplifier. This leads to a prolongation access time in the write operation and thus is not desirable.
Note, the problems in the prior art will be explained later in detail in contrast with the preferred embodiment of the present invention.